Uart/Sio Serial Status And Data Register Ch. N (Ssrn) - Fujitsu 8FX Hardware Manual

MB95630H Series
22.7.3 UART/SIO Serial Status and Data Register ch. n
(SSRn)
The UART/SIO serial status and data register ch. n (SSRn) indicates the
transmission/reception status and error status of the UART/SIO.
■ Register Configuration
bit 7
Field —
Attribute —
Initial value 0
■ Register Functions
[bit7:6] Undefined bits
Their read values are always "0". Writing values to these bits has no effect on operation.
[bit5] PER: Parity error flag bit
This bit detects the parity error in receive data.
This bit is set to "1" when a parity error occurs during a receive operation reception. Writing "0" to the RERC
bit in the SMC2n register clears this bit.
When a parity error is detected at the same time as clearing this bit by writing "0" to the RERC bit, setting
this bit to "1" is given priority.
bit5
Reading "0"
Reading "1"
[bit4] OVE: Overrun error flag bit
This bit detects the overrun error in receive data.
This bit is set to "1" when an overrun error occurs during a receive operation reception. Writing "0" to the
RERC bit in the SMC2n register clears this bit.
When an overrun error is detected at the same time as clearing this bit by writing "0" to the RERC bit, setting
this bit to "1" is given priority.
bit4
Reading "0"
Reading "1"
[bit3] FER: Framing error flag bit
This bit detects the framing error in receive data.
This bit is set to "1" when a framing error occurs during a receive operation reception. Writing "0" to the
RERC bit in the SMC2n register clears this bit.
When a framing error is detected at the same time as clearing this bit by writing "0" to the RERC bit, setting
this bit to "1" is given priority.
bit3
Reading "0"
Reading "1"
MN702-00009-2v0-E
6 5
— PER
— R
0 0
Indicates that no parity error has occurred.
Indicates that a parity error has occurred.
Indicates that no overrun error has occurred.
Indicates that an overrun error has occurred.
Indicates that no framing error has occurred.
Indicates that a framing error has occurred.
FUJITSU SEMICONDUCTOR LIMITED
4 3
OVE FER
R R
0 0
Details
Details
Details
CHAPTER 22 UART/SIO
22.7 Registers
2 1
RDRF TCPL
R R/W
0 0
0
TDRE
R
1
481