Configuration - Fujitsu 8FX Hardware Manual

MB95630H Series
19.2

Configuration

This section describes the configuration of the 16-bit PPG timer.
The number of pins and that of channels of the 16-bit PPG vary among products. For details,
refer to the device data sheet.
In this chapter, "n" represents the channel number. For details of pin names, register names and
register abbreviations of a product, refer to the device data sheet.
■ Block Diagram of 16-bit PPG Timer
When upper 8 bits of duty
setting register are written
but lower 8 bits are not
written, the value is "1",
otherwise it is "0".
CKS02
1 MCLK
MCLK/2
MCLK/4
MCLK/8
Prescaler
MCLK/16
MCLK/32
F /2 7 or F
CH CRH
8
F /2 or F
CH CRH
● Count clock selector
The clock for the countdown of 16-bit downcounter is selected from eight types of internal
count clocks.
● 16 bit downcounter
It counts down with the count clock selected with the count clock selector.
MN702-00009-2v0-E
Figure 19.2-1 Block Diagram of 16-bit PPG Timer
16-bit PPG cycle
setting buffer register
(upper 8 bits) ch. n
CKS01
CKS00
16-bit PPG cycle setting
buffer register ch. n
upper 8 bits buffer
1
CLK
16-bit
downcounter
/2 6 or F /2 6
MCRPLL
7 7
/2 or F /2
MCRPLL
STOP
START
Edge
detection
Pin
TRGn
EGS1 EGS0
STRG CNTE RTRG
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 19 16-BIT PPG TIMER
16-bit PPG cycle
setting buffer register
16-bit PPG duty
(lower 8 bits) ch. n
setting buffer register
(upper 8 bits) ch. n
16-bit PPG duty
setting buffer register ch. n
for upper 8 bits buffer
0
Comparator
LOAD
BORROW
S
R
19.2 Configuration
16-bit PPG duty
setting buffer register
(lower 8 bits) ch. n
16-bit PPG duty
setting buffer register ch. n
for lower 8 bits buffer
circuit
MDSE PGMS OSEL POEN
Q
Interrupt
selection
IRS1 IRS0 IRQF IREN
POEN
Pin
PPGn
Interrupt
of 16-bit PPG
335