Watchdog Timer Control Register (Wdtc) - Fujitsu 8FX Hardware Manual

MB95630H Series
8.4.1

Watchdog Timer Control Register (WDTC)

The watchdog timer control register (WDTC) activates or clears the watchdog
timer.
■ Register Configuration
bit 7
Field CS1
Attribute and initial values for software watchdog timer
Attribute R/W
Initial value 0
Attribute and initial values for hardware watchdog timer
Attribute R
Initial value 0
■ Register Functions
[bit7:6] CS[1:0]: Count clock switch bits
[bit5] CSP: Count clock select sub-CR selector bit
These bits select the count clock of the watchdog timer.
Write to these bits at the same time as activating the watchdog timer by the watchdog control bits.
No change can be made once the watchdog timer is activated.
bit7 bit6
Writing 0 0
Writing 0 1
Writing 1 0
Writing 1 1
Writing 0/1 0/1
Note: Since the time-base timer is stopped in subclock mode or sub-CR clock mode, always select the output
of the watch prescaler in subclock mode.
[bit4] HWWDT: Hardware watchdog timer start bit
This is a read-only bit used to confirm the start/stop of the hardware watchdog timer.
bit4
Reading "0"
Reading "1"
MN702-00009-2v0-E
CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER
6 5
CS0 CSP
R/W R/W
0 0
R R
0 1
(F : main clock, F
bit5
CH
0 Output cycle of time-base timer (2
0
Output cycle of time-base timer (2
0
Output cycle of watch prescaler (2
0
Output cycle of watch prescaler (2
1
Output cycle of sub-CR timer (2
Indicates that the hardware watchdog timer has stopped (The software watchdog timer can be
activated).
Indicates that the hardware watchdog timer has been activated.
FUJITSU SEMICONDUCTOR LIMITED
4 3
HWWDT WTE3
R W
0 0
R W
1 0
Details
: main CR clock, F
CRH
F : subclock, F : sub-CR clock)
CL CRL
21 20
/F , 2
CH
20 19
/F , 2
CH
14
/F or 2
CL
13
/F or 2
CL
16
/F )
CRL
Details
8.4 Register
2 1
WTE2 WTE1
W W
0 0
W W
0 0
: main CR PLL clock,
MCRPLL
20
/F or 2 /F )
CRH MCRPLL
19
/F or 2 /F )
CRH MCRPLL
13
/F )
CRL
12
/F )
CRL
0
WTE0
W
0
W
0
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