Watchdog Timer Control Register (Wdtc) - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 11 WATCHDOG TIMER
11.3.1

Watchdog Timer Control Register (WDTC)

The watchdog timer control register (WDTC) activates or clears the watchdog timer.
Watchdog Timer Control Register (WDTC)
Address
bit7
000C
CS1
H
R/W
R/W : Readable/writable (Read value is the same as write value)
R0,W : Write only (Writable, "0" is read)
R0/WX : Undefined bit (Read value is "0", writting has no effect on operation)
- : Not used
: Initial value
F : Main clock
CH
F : Subclock
CL
176
Figure 11.3-2 Watchdog Timer Control Register (WDTC)
bit6 bit5 bit4
CS0 - -
R/W R0/WX R0/WX
WTE3 WTE2 WTE1 WTE0
0 1 0
Other than above
CS1 CS0
0 0
0 1
1 0
1 1
bit3 bit2 bit1
WTE3 WTE2 WTE1
R0,W R0,W R0,W
Watchdog control bits
• Activate watchdog timer
(in first write after reset)
1
• Clear watchdog timer
(in second or succeeding write after reset)
No effect on operation
Count clock switch bits
Output cycle of timebase timer (2
Output cycle of timebase timer (2
Output cycle of watch prescaler (2
Output cycle of watch prescaler (2
Initial value
bit0
WTE0 00--0000
B
R0,W
21
/F )
CH
20
/F )
CH
14
/F )
CL
13
/F )
CL