Fujitsu F2MC-8FX Hardware Manual page 65

the PLL oscillation stabilization wait time to elapse after a request for state transition from PLL oscillation
stopped state to oscillation start is generated via an interrupt in standby mode or a change of clock mode by
software. Note that the PLL clock oscillation stabilization wait time changes according to the PLL startup
timing.
Table 6.2-2 shows the PLL oscillation stabilization wait time.
Table 6.2-2 PLL Oscillation Stabilization Wait Time
Main PLL clock
Oscillation Stabilization Wait Time and Clock Mode/Standby Mode Transition
The clock controller automatically waits for the oscillation stabilization wait time to elapse as needed when
the operating state causes a transition. Depending on the state transition, however, the clock controller does
not always wait for the oscillation stabilization wait time.
For details on state transitions, see "6.7 Clock Modes" and "6.8 Operations in Low-power Consumption
Modes (Standby Modes)".
PLL Oscillation Stabilization Wait Time
Minimum time Maximum time
11 11
2 /F x 2 2
CH
• Stabilization wait time is taken while 2
/F x 3
twice (minimum) or three times (maximum).
CH
• F represents the main clock frequency.
CH
CHAPTER 6 CLOCK CONTROLLER
Remarks
11
/F is counted
CH
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