Uart/Sio Dedicated Baud Rate Generator Prescaler Selection Register (Pssr) - Fujitsu F2MC-8FX Hardware Manual

21.3.1 UART/SIO Dedicated Baud Rate Generator Prescaler
Selection Register (PSSR)
The UART/SIO dedicated baud rate generator prescaler register (PSSR) controls the
output of the baud rate clock and the prescaler.

UART/SIO Dedicated Baud Rate Generator Prescaler Selection Register (PSSR)

Figure 21.3-2 UART/SIO Dedicated Baud Rate Generator Prescaler Selection Register (PSSR)
Address
0FBE
H
R/W:
R0/WX:
Table 21.3-1 UART/SIO Dedicated Baud Rate Generator Prescaler Selection Register (PSSR)
Bit name
bit7 to 3 Unused
BRGE:
bit2 Baud rate clock output
enable
PSS1, 0:
bit1, 0
Prescaler selection
CHAPTER 21 UART/SIO DEDICATED BAUD RATE GENERATOR
bit7 bit6 bit5
- -
PSSR0
R0/WX R0/WX R0/WX
PSS1 PSS2
0
0
1
1
BRGE
0
1
Readable/writable (Read value is the same as write value)
Undefined bit (Read value is "0", writting has no effect on operation)
: Initial value
These bits are not used. Reading the bits always returns "0".
• This bit enables the output of the baud rate clock "BRCLK".
Setting the bit to "1" loads BRS[7:0] to the 8-bit down-counter and outputs "BRCLK", which is
supplied to the UART/SIO.
Setting the bit to "0" stops the output of "BRCLK".
PSS1 PSS0
0
0
1
1
bit4 bit3 bit2
- - -
BRGE PSS1
R0/WX R0/WX R/W
Prescaler selection
1/1
0
1 1/2
1/4
0
1/8
1
Baud rate clock output enable
Disables baud rate output
Enable baud rate output
Function
Prescaler selection
0 1/1
1 1/2
0 1/4
1 1/8
Initial value
bit1 bit0
00000000
PSS0
R/W R/W
B
365