Fujitsu F2MC-8FX Hardware Manual page 401

2
Table 22.5-3 I C Bus Status Register (IBSR0)
Bit name
BB:
bit7
Bus busy bit
RSC:
bit6 Repeated start
condition detection bit
bit5 Unused bit
LRB:
Acknowledge
bit4
storage bit
TRX:
bit3
Data transfer status bit
AAS:
bit2 Addressing detection
bit
GCA:
bit1 General call address
detection bit
FBT:
bit0
First byte detection bit
This bit indicates the bus status.
• This bit is set to "1" when a start condition is detected.
• This bit is set to "0" when a stop condition is detected.
This bit is used to detect repeated start conditions.
• This bit is set to "1" when a repeated start condition is detected.
• This bit is set to "0" in the following cases:
- When "0" is written to IBCR10:INT.
- When the slave address does not match the address set in IAAR0 in slave mode.
- When the slave address matches the address set in IAAR0 but IBCR00:AACKX = 1 in slave
mode.
- When the general call address is received but IBCR10:GACKE = 0 in slave mode.
- When a stop condition is detected.
The value read is always "0".
An attempt to write to the bit is meaningless.
This bit saves the value of the SDA0 line in the ninth shift clock cycle during data byte transfer.
• This bit is set to "1" when no acknowledgment is detected (SDA0 = H).
• This bit is set to "0" in the following cases:
- When acknowledgment is detected (SDA0 = L)
- When a start or stop condition is detected.
Note: It follows from the above that this bit must be read after ACK. (Read the value in response
to the transfer completion interrupt in the ninth SCL0 cycle.) Accordingly, if ACK is read
when the IBCR00:INTS bit is "1", you must write "0" to the IBCR00:INTS bit in the
transfer completion interrupt triggered by the eighth SCL0 cycle so that another transfer
completion interrupt will be triggered by the ninth SCL0 cycle.
This bit indicates the data transfer mode.
• This bit is set to "1" when data transfer is performed in transfer mode.
• This bit is set to "0" in the following cases:
- Data is transferred in receive mode.
- NACK is received in slave transmit mode.
This bit indicates that the MCU has been addressed in slave mode.
• This bit is set to "1" if the MCU is addressed in slave mode.
• This bit is set to "0" when a start or stop condition is detected.
This bit is used to detect a general call address.
• This bit is set to "1" in the following cases:
- When the general call address (00
- When the general call address (00
- When arbitration lost is detected during transmission of the second byte of the general call
address in master mode.
• This bit is set to "0" in the following cases:
- When a start or stop condition is detected.
- When arbitration lost is not detected during transmission of the second byte of the general call
address in master mode.
This bit is used to detect first byte.
• This bit is set to "1" when a start condition is detected.
• This bit is set to "0" in the following cases:
- When "0" is written to the IBCR10:INT bit.
- When the slave address does not match the address set in IAAR0 in slave mode.
- When the slave address matches the address set in IAAR0 but IBCR00:AACKX = 1 in slave
mode.
- When the general call address is received with IBCR10:GACKE = 0 in slave mode.
Function
) is received in slave mode.
H
) is received in master mode with IBCR10:GACKE = 1.
H
2
CHAPTER 22 I C
387