I 2 C Data Register (Iddr0) - Fujitsu F2MC-8FX Hardware Manual

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CHAPTER 22 I C
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22.5.3 I C Data Register (IDDR0)
The IDDR0 register is used to set the data or address to send and to hold the data or
address received.
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I C Data Register (IDDR0)
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I C data register (IDDR0)
Address
0063 IDDR0
H
R/W: Readable/writable (Read value is the same as write value)
In transmit mode, each bit of the data or address value written to the register is shifted to the SDA0 line,
starting with the MSB. The write side of this register is double-buffered, where if the bus is in use
(IBSR0:BB=1), the write data is loaded to the 8-bit shift register either when the current data transfer
completion interrupt is cleared (writing "0" to the IBCR10:INT bit) or when a repeated start condition is
generated (writing "1" to the IBCR10:SCC bit). Each bit of the shift register data is output (shifted) to the
SDA0 line. Note that writing to this register has no effect on the current data transfer. In slave mode,
however, data is transferred to the shift register after the address is determined.
The received data or address can be read from this register during the transfer completion interrupt
(IBCR10:INT = 1). When it is read, however, the serial transfer register is directly read from, the receive
data is valid only while IBCR10:INT = 1.
388
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Figure 22.5-5 I C Data Register (IDDR0)
bit7 bit6 bit5
D7 D6 D5
R/W R/W R/W R/W
bit4 bit3 bit2 bit1
D4 D3 D2
R/W R/W R/W
bit0 Initial value
D1 D0 00000000
R/W
B