Second Register (Secr) - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 27 REAL TIME CLOCK
27.3.7

Second register (SECR)

The Second Register is used to hold the second information.
Second Register (SECR)
SECR (Real time clock second register)
Address
0FF6
* R/W : Readable and writable, - : Unused, X : Indeterminate
R0/WX : Read 0 and write has no effect on operation
This register holds the updated second value in binary form. During reading the current value in second
counter is read. The most significant 2 bits read as "00". In order to have proper operation, second value
must be adequately set between 00H (000000B or 0 second) and 3BH (111011B or 59 second) inclusive.
please note that only the latched value (not the value being continuously updated in the counters) is read
from register while RTCCRL:CL is equal to "1".
500
Figure 27.3-8 Second Register (SECR)
Bit 7 Bit 6 Bit 5
- -
SEC5
H
R0/WX R0/WX R/W
Bit 4 Bit 3 Bit 2 Bit 1
SEC4 SEC3 SEC2 SEC1
R/W R/W R/W R/W
Bit 0 Initial value
SEC0 00XXXXXX
B
R/W