Fujitsu F2MC-8FX Hardware Manual page 393

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Table 22.5-1 I C Bus Control Register 0 (IBCR00) (1 / 2)
Bit name
AACKX:
bit7 Address acknowledge
disable bit
INTS:
Timing select bit for
bit6
data reception transfer
completion flag (INT)
ALF:
Arbitration lost
bit5
interrupt request flag
bit
ALE:
bit4 Arbitration lost
interrupt enable bit
SPF:
bit3 Stop detection interrupt
request flag bit
This bit controls the address ACK when the first byte is transmitted.
Setting the bit to "0": Causes the address ACK to be output automatically. (The address ACK is
returned automatically if the slave address matches.)
Setting the bit to "1": Prevents the address ACK from being output.
• Write "1" to this bit in either of the following ways:
- Write "1" to the bit in master mode.
- Clear the bit to "0" after making sure that the bus busy bit is "0" (IBSR0:BB = 0).
Note: • If AACKX = "1" and IBSR0:FBT = "0" when an IBCR10:INT bit interrupt occurs, no address
ACK is output even though the I
bit to "0" as an interrupt is generated upon completion of transfer of each byte of address/data
in the same way as during addressing.
• If AACKX = "1" and IBSR0:FBT = "1" when an IBCR10:INT bit interrupt occurs, "1" might
be written to AACKX after addressing as in slave mode. Either continue normal
communication after setting AACKX to 0 again or restart communication after disabling I
operation (ICCR0:EN = 0).
This bit selects the timing of the transfer completion interrupt (IBCR10:INT) when data is received.
Change the bit only when IBSR0:TRX = 0 and IBSR1:FBT = 0.
Setting the bit to "0": Sets the transfer completion interrupt (IBCR10:INT) in the ninth SCL cycle.
Setting the bit to "1": Sets the transfer completion interrupt (IBCR10:INT) in the eighth SCL cycle.
Note: • The transfer completion interrupt (IBCR10:INT) is set always in the ninth SCL0 cycle except
during data reception (IBSR1:TRX = 1 or IBSR1:FBT = 1).
• If the data ACK depends on the content of the received data (such as packet error checking
used by the SM bus), control the data ACK by setting the data ACK enable bit
(IBCR10:DACKE) after writing "1" to this bit (for example, using a previous transfer
completion interrupt) to read latest received data.
• The latest data ACK (IBSR0:LRB) can be read after the ACK has been received (IBSR0:LRB
must be read during the transfer completion interrupt in the ninth SCL cycle.) If ACK is read
when this bit is "1", therefore, you must write "0" to this bit in the transfer completion
interrupt in the eighth SCL0 cycle so that another transfer completion interrupt will occur in
the ninth SCL0 cycle.
This bit is used to detect when arbitration is lost.
• An arbitration lost interrupt request is generated if this bit and the IBCR00:ALE bit are both "1".
• This bit is set to "1" in the following cases:
- When arbitration lost is detected during data/address transmission as a master
- When "1" is written to the IBCR10:MSS bit with the bus being used by another system. However, the
bit is not set when "1" is written to the MSS bit after the system returns AACK or GCAK as a slave.
• This bit is set to "0" in the following cases:
- When "0" is written to the IBCR00:ALF bit with IBSR0:BB = 0.
- When "0" is written to the IBCR10:INT bit to clear the transmission completion flag.
• Writing "1" to this bit leaves its value unchanged and has no effect on the operation.
• The bit returns "1" when read by a read-modify-write operation.
This bit enables or disables arbitration lost interrupts.
• An arbitration lost interrupt request is generated if this bit and the IBCR00:ALF bit are both "1".
Setting the bit to "0": Disables arbitration lost interrupts.
Setting the bit to "1": Enables arbitration lost interrupts.
This bit is used to detect a stop condition.
• A stop detection interrupt request is generated if this bit and the IBCR00:SPE bit are both "1".
• This bit is set to "1" if a valid stop condition is detected when the bus is busy.
Setting the bit to "0": Clears itself (changes the value to "0").
Setting the bit to "1": Leaves its value unchanged without affecting the operation.
• The bit returns "1" when read by a read-modify-write operation.
Function
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C address matches the slave address. Clear the IBCR10:INT
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CHAPTER 22 I C
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