Fujitsu F2MC-8FX Hardware Manual page 63

F2mc-8fx 8-bit microcontroller
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Combinations of Clock Mode and Standby Mode
Table 6.1-4 lists the combinations of clock mode and standby mode and their respective operating states of
internal circuits.
Table 6.1-4 Combinations of Standby Mode and Clock Mode and Internal Operating States
Function
Main
Main
PLL
clock
clock
mode
mode
Main clock
Operating
Main PLL
Stopped
Operat-
clock
*1
ing
Subclock
Operating*2
CPU
Operating
ROM
Operating
RAM
I/O ports
Operating
Timebase timer
Operating
Watch
Operating*2
prescaler
Watch counter
Operating*2
External
Operating
interrupt
Watchdog
Operating
timer
Low-voltage
Operating
detection reset
Other
peripheral
Operating
resources
*1:
Operates when the main PLL clock oscillation enable bit in the PLL control register (PLLC:MPEN)
is set to "1".
*2:
Stops when the subclock oscillation stop bit in the system clock control register (SYCC:SUBS) is set
to "1".
*3:
Watch counter keeps counting and no interrupts occur. When the subclock oscillation stop bit in the
system clock control register (SYCC: SUBS) is set to "1", watch counter stops.
RUN
Sub clock mode
Main
(Two-system
clock
clock product)
mode
Stopped
Operating
Stopped
Stopped
*1
Operating
Operating*2
Operating
Stopped
Operating
Value held
Operating
Output held
Stopped
Operating
Operating
Operating*2
Operating
Operating*2
Operating
Operating
Operating
Stopped
Operating
Operating
Operating
Operating
Sleep
Main
Sub clock mode
Main
PLL
(Two-system
clock
clock
clock product)
mode
mode
Stopped
Operat-
Stopped
ing
Operating
Stopped
Value held
Output held
Stopped
Operating
Operating
Operating
Stopped
Operating
Operating
CHAPTER 6 CLOCK CONTROLLER
Watch (Two-
Timebase
system clock
Timer
product)
Main
Sub clock mode
PLL
(Two-system
clock
clock product)
mode
Operating
Stopped
Stopped*1
Stopped
Operating*2
Operating
Stopped
Stopped
Value held
Value held
Output held
Output held
Operating
Stopped
Operating*2
Operating
Operating*2
Operating
Operating
Operating
Stopped
Stopped
Operating
Operating
Stopped
Stopped
Stop
Main PLL clock
mode
Stopped Stopped
Stopped Stopped
Operat-
Stopped
ing*2
Stopped Stopped
Value
Value
held
held
Output
Output
held/
held/Hi-
Hi-Z
Z
Stopped Stopped
Operat-
Stopped
ing*2
Operat-
Stopped
ing*3
Operat-
Operat-
ing
ing
Stopped Stopped
Operat-
Operat-
ing
ing
Stopped Stopped
49

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