System Clock Control Register (Sycc) - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 6 CLOCK CONTROLLER
6.3

System Clock Control Register (SYCC)

The system clock control register (SYCC) is used to indicate and switch the current clock
mode, select the machine clock divide ratio, and control subclock oscillation in main clock
mode and main PLL clock mode.
Configuration of System Clock Control Register (SYCC)
Figure 6.3-1
Address
0007
H
R/WX : Read only (Readable, writting has no effect on operation)
R/W : Readable/writable (Read value is the same as write value)
X : Indeterminate
: Initial value
52
Configuration of System Clock Control Register (SYCC)
bit7 bit6 bit5
SCM1 SCM0
SCS1
R/WX R/WX R/W
bit4
bit3 bit2
SCS0 SRDY SUBS
R/W R/WX R/W
DIV1 Machine clock divide ratio selection bits
DIV0
0 0 Source clock
0 1 Source clock / 4
1 0 Source clock / 8
1 1 Source clock /16
SUBS Subclock oscillation stop bit
0 Starts subclock oscillation
1 Stops subclock oscillation
SRDY Subclock oscillation stability bit
Indicates the subclock oscillation stabilization
0
wait state or subclock oscillation being stopped
1 Indicates subclock oscillation being stable
SCS1
SCS0
0 0 Subclock mode
Setting prohibited
0 1
1 0 Main clock mode
1 1 Main PLL clock mode
SCM1 Clock mode monitor bits
SCM0
0 0 Subclock mode
0 1 Meaningless
1 0 Main clock mode
1 1 Main PLL clock mode
Initial value
bit1 bit0
1010x011
DIV1 DIV0
R/W R/W
Cock mode selection bits
B