Fujitsu F2MC-8FX Hardware Manual page 397

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Table 22.5-2 I C Bus Control Register 1 (IBCR10) (1 / 2)
Bit name
BER:
bit7 Bus error interrupt
request flag bit
BEIE:
bit6 Bus error interrupt
request enable bit
SCC:
bit5 Start condition
generation bit
MSS:
bit4
Master/slave select bit
DACKE:
bit3 Data acknowledge
enable bit
GACKE:
bit2 General call address
acknowledge enable bit
INTE:
bit1 Transfer completion
interrupt enable bit
This bit is used to detect bus errors.
• A bus error interrupt request is generated if this bit and the IBCR10:BEIE bit are both "1".
• This bit is set to "1" when an invalid start or stop condition is detected.
Setting the bit to "0": Clears itself (changes the value to "0").
Setting the bit to "1": Leaves its value unchanged without affecting the operation.
• The bit returns "1" when read by a read-modify-write operation.
• When this bit is set to "1", ICCR0:EN is set to "0", and the I
terminate data transfer.
This bit enables or disables bus error interrupts.
• A bus error interrupt request is generated if this bit and the IBCR10:BER bit are both "1".
Setting the bit to "0": Disables bus error interrupts.
Setting the bit to "1": Enables bus error interrupts.
This bit can be used to generate a start condition repeatedly to restart communications in master
mode.
• Writing "1" to the bit in master mode generates a start condition repeatedly.
• Writing "0" to the bit is meaningless.
• When read, the bit returns "0".
Note: • Do not set IBCR10:SCC = 1 and IBCR10:MSS = 0 at the same time.
• An attempt to write "1" to this bit is ignored when IBCR10:INT = 0 (no start condition is
generated). If you write "1" to this bit and "0" to the IBCR10:INT bit at the same time
when the IBCR10:INT = 1, this bit takes priority and generates a start condition.
This bit selects master mode or slave mode.
• Writing "1" to this bit while the I
generates a start condition, and then starts address transfer.
• Writing "0" to the bit while the I
generates a stop condition, and then ends data transfer.
• If arbitration lost occurs during data or address transfer in master mode, this bit is cleared to "0"
and the mode changes to slave mode.
Note: • Do not set IBCR10:SCC = 1 and IBCR10:MSS = 0 at the same time.
• An attempt to write "0" to this bit is ignored when IBCR10:INT = 0. If you write "0" to
this bit and "0" to the IBCR10:INT bit at the same time when the IBCR10:INT = 1, this
bit takes priority and generates a stop condition.
• The IBCR00:ALF bit is not set even though you write "1" to the MSS bit during
transmission or reception in slave mode. Do not write "1" to the MSS bit during
transmission or reception in slave mode.
This bit controls data acknowledgment during data reception.
Setting the bit to "0": Disables data acknowledge output.
Setting the bit to "1": Enables data acknowledge output. In this case, data acknowledgment is
output in the ninth SCL0 cycle during data reception in master mode. In
slave mode, data acknowledgment is output in the ninth SCL0 cycle only if
address acknowledgment has already been output.
This bit controls general call address acknowledgment.
Setting the bit to "0": Disables output of general call address acknowledge.
Setting the bit to "1": Causes a general call address acknowledgment to be output if a general call
address (00
This bit enables or disables transfer completion interrupts.
Setting the bit to "0": Disables transfer completion interrupts.
Setting the bit to "1": Enables transfer completion interrupts.
• A transfer completion interrupt request is generated if this bit and the IBCR10:INT bit are both
"1".
Function
2
2
C bus is in the idle state (IBSR0:BB = 0) selects master mode,
2
C bus is in the busy state (IBSR0:BB = 1) selects slave mode,
) is received in master or slave mode.
H
CHAPTER 22 I
C interface enters halt mode to
2
C
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