Timebase Timer Mode - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 6 CLOCK CONTROLLER
6.8.4

Timebase Timer Mode

Timebase timer mode allows only the main clock oscillation, subclock oscillation,
timebase timer, and watch prescaler to work. The operating clock for the CPU and
peripheral resources is stopped in this mode.
Operations in Timebase Timer Mode
In timebase timer mode, main clock supply is stopped except for the timebase timer. The device stops all
the functions except timebase timer, external interrupt and low-voltage detection reset while retaining the
contents of registers and RAM that exist immediately before the transition to timebase timer mode.
You can however start or stop subclock oscillation by setting the subclock oscillation stop bit in the system
clock control register (SYCC: SUBS). When the subclock is oscillating, the watch prescaler and watch
counter operate.
Transition to timebase timer mode
Writing "1" to the watch bit in the standby control register (STBC:TMD) causes the device to enter
timebase timer mode if the system clock monitor bits in the system clock control register (SYCC: SCM1,
0) are "10" or "11".
The device can enter timebase timer mode only when the clock mode is main clock mode or main PLL
clock mode.
Upon transition to timebase timer mode, the states of external pins are retained when the pin state setting
bit in the standby control register (STBC:SPL) is "0", and the states of external pins become high
impedance when that bit is "1" (those pins are pulled up for which pull-up resistor connection has been
selected in the pull-up setting register).
Cancellation of timebase timer mode
The device is released from timebase timer mode in response to a reset, timebase timer interrupt, or
external interrupt.
You can start or stop subclock oscillation by setting the subclock oscillation stop bit in the system clock
control register (SYCC: SUBS). When the subclock is oscillating, you can also release the device from
timebase timer mode using an interrupt by the watch prescaler or watch counter.
Note:
When timebase timer mode is canceled via an interrupt, peripheral resources placed into timebase timer mode
during an action resume that action. Therefore, the initial interval time of the interval timer and other similar
settings are rendered indeterminate. After recovery from timebase timer mode, initialize each peripheral
resource as necessary.
74