CHAPTER 16 8/16-BIT COMPOSITE TIMER
Figure 16.15-2 Operations of Counter in Standby Mode or in Pause (Serving as PWM Timer)
(FF
)
Counter value
H
FF
H
00
H
Time
Delay of oscillation stabilization wait time
T00/01DR value (FF
)
H
STA bit
*
PWM timer output pin
Sleep mode
Maintains the level prior to stop
Maintains the level prior to hold
SLP bit
(STBC register)
Wake-up from stop mode by external interrupt
Wake-up from sleep mode by interrupt
STP bit
(STBC register)
HO bit
*: The PWM timer output maintains the value held before it enters the stop mode.
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