Fujitsu F2MC-8FX Hardware Manual page 60

CHAPTER 6 CLOCK CONTROLLER
The clock controller consists of the following blocks:
Main clock oscillator circuit
This block is the oscillator circuit for the main clock.
Subclock oscillator circuit (Two-system clock product)
This block is the oscillator circuit for the subclock.
Main PLL oscillator circuit
This block is the oscillator circuit for the main PLL.
System clock selector
This block selects one of the three different source clocks for main clock, subclock and main PLL clock
depending on the clock mode. The prescaler frequency-divides the selected source clock into the machine
clock. It is supplied to the clock control circuit.
Clock control circuit
This block controls the supply of the machine clock to the CPU and each peripheral resource according to
the standby mode or oscillation stabilization wait time.
Oscillation stabilization wait circuit
This block outputs the oscillation stabilization wait time signal for each clock from 14 types of main-clock
oscillation stabilization signals created by the timebase timer and 15 types of subclock oscillation
stabilization signals created by the watch prescaler.
System clock control register (SYCC)
This register is used to control current clock mode display, clock mode selection, machine clock divide
ratio selection, and subclock oscillation in main clock mode and main PLL clock mode.
Standby control register (STBC)
This register is used to control the transition from RUN state to standby mode, the setting of pin states in
stop mode, timebase timer mode, or watch mode, and the generation of software resets.
PLL control register (PLLC)
This register is used to enable/disable the oscillation of the main PLL clock, set the multiplier, and to
indicate the stability of PLL oscillation.
Oscillation stabilization wait time setting register (WATR)
This register is used to set the oscillation stabilization wait time for the main clock and subclock.
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