Interrupts Of 16-Bit Ppg Timer - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 17 16-BIT PPG TIMER
17.6

Interrupts of 16-bit PPG Timer

The 16-bit PPG timer can generate interrupt requests in the following cases:
• When a trigger or counter borrow occurs
• When a rising edge of PPG is generated in normal polarity
• When a falling edge of PPG is generated in inverted polarity
The interrupt operation is controlled by IRS1 (bit 3) and IRS0 (bit2) in the PCNTL register.
Interrupts of 16-bit PPG Timer
Table 17.6-1 shows interrupt control bits and interrupt sources of the 16-bit PPG timer.
Table 17.6-1 Interrupt Control Bits and Interrupt Sources of 16-bit PPG Timer
Interrupt flag bit
Interrupt request enable bit
Interrupt type select bits
Interrupt sources
When IRQF (bit 4) in the 16-bit PPG status control register (PCNTL0) is set to "1" and interrupt requests
are enabled (PCNTL0:IREN: bit 5 = "1") in the 16-bit PPG timer, an interrupt request is generated and
outputted to the controller.
Registers and Vector Table Related to Interrupts of 16-bit PPG Timer
Table 17.6-2 Registers and Vector Table Related to Interrupts of 16-bit PPG Timer
Interrupt
source
ch.0~ch.7
ch: Channel
"APPENDIX B Table of Interrupt Causes" shows the interrupt request numbers and vector tables for all
peripheral functions.
292
Item
PCNTL0:IRQF
PCNTL0:IREN
PCNTL0:IRS1, 0
PCNTL0:IRS1, 0="00"
Hardware trigger by TRG Pin input of 16-bit down-counter, software trigger and
retrigger
PCNTL0:IRS1, 0="01"
Counter borrow of 16-bit down-counter
PCNTL0:IRS1, 0="10"
Rising edge of PPG0 output in normal polarity, or falling edge of PPG0 output in
inverted polarity
PCNTL0:IRS1, 0="11"
Counter borrow of 16-bit down-counter, rising edge of PPG0 output in normal
polarity, or falling edge of PPG0 output in inverted polarity
Interrupt level setting register
Interrupt
request No.
IRQ23
Description
Register Setting bit
ILR5 L23
Vector table address
Upper Lower
FFCC FFCD
H H