Clock Supervisor Control Register (Csvcr) - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 26 CLOCK SUPERVISOR
26.3.1

Clock Supervisor Control Register (CSVCR)

The clock supervisor control register (CSVCR) is used to enable the various functions
and to check the status.
Clock Supervisor Control Register (CSVCR)
bit
Address
000FEA
H
R/W
R
Reserved
474
Figure 26.3-2 Clock Supervisor Control Register (CSVCR)
7 6 5
MM SM RCE
Reserved
R/W R R
Reserved
SRST
*: Assuming that a sub clock halt has been already detected at transition from
SSVE
MSVE
Reserved
: Readable/writable
: Read only
: Reserved bit
: Initial value
4 3 2
MSVE SSVE SRST
R/W R/W R/W R/W
0
Be sure to set this bit to "0".
Reset generation enable bit
0
Disables reset generation.
1
Enables reset generation.
main mode to sub mode.
Sub clock monitoring enable bit
0
Disables sub clock monitoring.
1
Enables sub clock monitoring.
Main clock monitoring enable bit
0
Disables main clock monitoring.
1
Enables main clock monitoring.
RCE
CR clock oscillation enable bit
0
Disables CR clock oscillation.
1
Enables CR clock oscillation.
SM
Sub clock halt detection bit
0
Sub clock halt not detected.
1
Sub clock halt detected.
MM
Main clock halt detection bit
0
Main clock halt not detected.
1
Main clock halt detected.
0
Be sure to set this bit to "0".
1 0
Initial value
Reserved
00011100
R/W
Reserved bit
*
Reserved bit
B