Fujitsu F2MC-8FX Hardware Manual page 52

CHAPTER 5 CPU
Carry flag (C)
This flag is set to "1" when a carry from bit 7 or a borrow to bit 7 occurs as the result of an operation.
Otherwise, the flag is set to "0". When a shift instruction is executed, the flag is set to the shift-out value.
Figure 5.1-6 shows how the carry flag is updated by a shift instruction.
• Left-shift (ROLC)
bit7
C
Interrupt Acceptance Control Bits
Interrupt enable flag (I)
When this flag is set to "1", interrupts are enabled and accepted by the CPU. When this flag is set to "0",
interrupts are disabled and rejected by the CPU.
The initial value after a reset is "0".
The SETI and CLRI instructions set and clear the flag to "1" and "0", respectively.
Interrupt level bits (IL1, IL0)
These bits indicate the level of the interrupt currently accepted by the CPU.
The interrupt level is compared with the value of the interrupt level setting register (ILR0 to ILR5) that
corresponds to the interrupt request (IRQ0 to IRQ23) of each peripheral resource.
The CPU services an interrupt request only when its interrupt level is smaller than the value of these bits
with the interrupt enable flag set (CCR: I = 1). Table 5.1-3 lists interrupt level priorities. The initial value
after a reset is "11
Table 5.1-3 Interrupt Levels
IL1
0
0
1
1
The interrupt level bits (IL1, IL0) are usually "11
program running).
For details on interrupts, see 8.1 Interrupts.
38
Figure 5.1-6 Carry Flag Updated by Shift Instruction
".
B
IL0 Interrupt Level
0 0
1 1
0 2
1 3
• Right-shift (RORC)
bit0 bit7
" with the CPU not servicing an interrupt (with the main
B
bit0
C
Priority
High
Low (No interrupt)