Explanation Of Hardware Watchdog Timer Operations And Setup Procedure Example - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 12 HARDWARE WATCHDOG TIMER
12.4 Explanation of Hardware Watchdog Timer Operations and
Setup Procedure Example
The hardware watchdog timer generates a hardware watchdog reset when the hardware
watchdog timer counter overflows.
Operations of Hardware Watchdog Timer
How to activate the hardware watchdog timer
• The timer of the hardware watchdog timer is activated after reset.
• A reset is the only way to stop its operation.
Clearing the hardware watchdog timer
• When the counter of the hardware watchdog timer is not cleared within the interval time, it overflows,
allowing the hardware watchdog timer to generate a hardware watchdog reset.
• The counter of the hardware watchdog timer is cleared when "0101
watchdog control bits of the watchdog timer control register (HWDC:WTE3 to WTE0) for the second or
any succeeding time.
• The hardware watchdog timer is cleared at the same time as the timer selected as the count clock (from
RC oscillator prescalar) is cleared.
Operation in standby mode
Regardless of the clock mode selected, the hardware watchdog timer clears its counter and stops the
operation when entering a standby mode (sleep/stop/timebase timer/watch).
Once released from the standby mode, the timer restarts the operation.
Note:
The hardware watchdog timer is also cleared when the RC oscillator prescalar is cleared.
For this reason, the hardware watchdog timer cannot function as such, if the software is set to
clear the RC oscillator prescalar repeatedly during the interval time of the hardware watchdog
timer.
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