Fujitsu F2MC-8FX Hardware Manual page 420

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CHAPTER 22 I C
Notes on selecting the transfer complete timing
• The transfer complete timing select bit (IBCR00:INTS) is valid only during data reception
(IBSR10:TRX = 0 and IBSR10:FBT = 0).
• In cases other than data reception (IBSR10:TRX = 1 or IBSR10:FBT = 1), the transfer completion
interrupt (IBCR10:INT) is always generated in the ninth SCL0 cycle.
• If the data ACK depends on the content of the received data (such as packet error checking used by the
SM bus), control the data ACK by setting the data ACK enable bit (IBCR10:DACKE) after writing "1"
to the IBCR00:INTS bit (for example, using a previous transfer completion interrupt) to read latest
received data.
• The latest data ACK (IBSR0:LRB) can be read after the ACK has been received (IBSR0:LRB must be
read during the transfer completion interrupt in the ninth SCL0 cycle.) If ACK is read when the
IBCR0:INTS bit is "1", therefore, you must write "0" to the IBCR00:INTS bit in the transfer completion
interrupt in the eighth SCL0 cycle so that another transfer completion interrupt will occur in the ninth
SCL0 cycle.
Notes on using the MCU standby mode wakeup function
• Set IBCR00:WUE to "1" immediately prior to setting the MCU to stop or watch mode. Similarly, clear
IBCR00:WUE (by writing "0") after the MCU wakes up from stop or watch mode so that I
can restart as soon as possible.
• When a wakeup interrupt request occurs, the MCU wakes up after the oscillation stabilization wait time
elapses. To prevent the data loss immediately after wakeup, design the system so that the SCL0 rises as
the first cycle and the first bit must be transmitted as data after 100 μs (assuming a minimum oscillation
stabilization wait time of 100 μs) from the wakeup due to start of I
the falling edge of SDA0).
• During a MCU standby mode, the status flags, state machine, and I
retain the states they had prior to entering the standby mode. To prevent a hang-up of the entire I
system, make sure that IBSR0:BB = 0 before entering standby mode.
• The wakeup function does not support the transition of the MCU to stop or watch mode with IBSR0:BB
= 1. If the MCU enters stop or watch mode with IBSR0:BB = 1, a bus error will occur upon detection of
a start condition.
• In PLL stop mode, for example, the time from wakeup to the start of communication becomes longer
than in stop/watch mode by the PLL oscillation stabilization wait time as the PLL oscillation
stabilization wait time is required in addition to the oscillation stabilization wait time.
• To ensure correct operation of the I
wakes up from stop or watch mode, regardless of whether this occurs due to the I
the wakeup function for some other resource (such as an external interrupt).
406
2
C interface, always clear IBCR00:WUE to "0" after the MCU
2
C operation
2
C transmission (upon detection of
2 2
C bus outputs for the I C function
2
C wakeup function or
2
C bus