Fujitsu F2MC-8FX Hardware Manual page 363

Transmission in asynchronous clock mode
Use UART/SIO serial mode control register 1 (SMC10) to select the serial data direction (endian), parity/
non-parity, parity polarity, stop bit length, character bit length, and clock.
Either of the following two procedures can be used to initiate the transmission process:
• Set the transmission operation enable bit (TXE) to "1", and then write transmit data to the serial output
data register to start transmission.
• Write transmit data to the UART/SIO serial output data register, and then set the transmission operation
enable bit (TXE) to "1" to start transmission.
Transmit data is written to the UART/SIO serial output data register (TDR0) after it is checked that the
transmit data register empty (TDRE) bit set to "1".
When the transmit data is written to the UART/SIO serial output data register (TDR0), the transmit data
register empty (TDRE) bit is cleared to "0".
The transmit data is transferred from the UART/SIO serial output data register (TDR0) to the transmission
shift register, and the transmit data register empty (TDRE) is set to "1".
When the transmission interrupt enable bit (TIE) contains "1", a transmission interrupt occurs if the
transmit data register empty (TDRE) bit is set to "1". This allows the next piece of transmit data to be
written to the UART/SIO serial output data register (TDR0) by interrupt handling.
To detect the completion of serial transmission by transmission interrupt, set the transmission completion
interrupt enable bits as follows: TEIE = 0, TCIE = 1. Upon completion of transmission, the transmission
completion flag (TCPL) is set to 1 and a transmission interrupt occurs.
Both the transmission completion flag (TCPL) and the transmission data register empty flag (TDRE), when
transmitting data consecutively, are set at the position which the transmission of the last bit was completed
(it varies depending on the data length, parity enable, or stop bit length setting), as shown in Figure 20.7-14
below.
Note that modifying UART/SIO serial mode control register 1 (SMC10) during transmission may result in
unpredictable operation.
Figure 20.7-6 Transmission in Asynchronous Clock Mode (UART)
UO D5
TCPL
TDRE
Transmission
interrupt
D6 D7 P
When the STOP bit length is set to 1 bit
CHAPTER 20 UART/SIO
SP SP
When the STOP bit length is set to 2 bits
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