Fujitsu F2MC-8FX Hardware Manual page 256

CHAPTER 16 8/16-BIT COMPOSITE TIMER
Table 16.5-1 Functional Description of Each Bit of 8/16-bit Composite Timer 00/01 Control Status Register
0 (T00CR0/T01CR0) (2 / 2)
Bit name
bit3 F3, F2, F1, F0:
to Timer operation mode
bit0 select bits
242
These bits select the timer operation mode.
• The PWM timer function (variable-cycle mode; F3, F2, F1, F0 = "0100
T00CR0 (timer 00) register or T01CR0 (timer 01) register. In this case, the other register is set to
F3, F2, F1, F0 = "0100
B
STA="1").
• The MOD bit is set to "0" automatically when the timer set for 16-bit operation (TMCR0:MOD =
"1") starts operation (T00CR1/T01CR1:STA = 1) in the PWM timer function (variable-cycle
mode).
• Write access to these bits is nullified during timer operation (T00CR1/T01CR1:STA = "1").
F3 F2 F1
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 0 1
1 1 0
1 1 0
1 1 1
1 1 1
Function
" automatically when the timer starts operation (T00CR1/T01CR1:
F0 Timer operation mode select bits
0 Interval timer (one-shot mode)
1 Interval timer (continuous mode)
0 Interval timer (free-run mode)
1 PWM timer (fixed-cycle mode)
0 PWM timer (variable-cycle mode)
1 PWC timer (H pulse = rising to falling)
0 PWC timer (L pulse = falling to rising)
1 PWC timer (cycle = rising to falling)
0 PWC timer (cycle = falling to rising)
PWC timer
1
(R pulse = rising to falling; Cycle = rising to rising)
Input capture
0
(rising, free-run counter)
Input capture
1
(falling, free-run counter)
Input capture
0
(both edges, free-run counter)
Input capture
1
(rising, counter clear)
Input capture
0
(falling, counter clear)
Input capture
1
(both edges, counter clear)
") is set by either the
B