Notes On Use Of I 2 C - Fujitsu F2MC-8FX Hardware Manual

22.8 Notes on Use of I
This section summarizes notes on using the I
Notes on Use of I
Notes on setting I
• Operation of the I
(IBCR00 and IBCR10).
• Setting the master/slave select bit (IBCR10:MSS) (by writing "1") starts data transfer.
Notes on setting the shift clock frequency
• The shift clock frequency can be calculated by determining the m, n, and DMBP values using the Fsck
equation in Table 22.5-4.
• "DMBP=1" may not be selected if the value of n is 4 (ICCR0:CS2 = CS1 = CS = 0).
Notes on priority for simultaneous writes
• Contention between next byte transfer and stop condition
When "0" is written to IBCR10:MSS with IBCR10:INT cleared, the MSS bit takes priority and a stop
condition develops.
• Contention between next byte transfer and start condition
When "1" is written to IBCR10:SCC with IBCR10:INT cleared, the SCC bit takes priority and a start
condition develops.
Notes on setup using software
• Do not select a repeated start condition (IBCR10:SCC=1) and slave mode (IBCR10:MSS=0)
simultaneously.
• Execution cannot return from interrupt processing if the interrupt request enable bit is enabled
(IBCR10:BEIE=1/IBCR10:INTE=1) with the interrupt request flag bit (IBCR10:BER/IBCR10:INT)
containing "1". Be sure to clear the IBCR10:BER/IBCR10:INT bit.
• The following bits are cleared to "0" when I
- AACKX, INTS, and WOE bits in the IBCR00 register
- All the bits in the IBCR10 register except the BER and BEIE bits
- All bits in the IBSR0 register
Notes on data acknowledgment
In slave mode, a data acknowledgment is generated in either of the following cases:
- When the received address matches the value in the address register (IAAR0) and
IBCR00:AACKX = 0.
- When a general call address (00
2
C
2
C
2
C interface registers
2
C interface must be enabled (ICCR0:EN) before setting the I
2
C interface.
2
C operation is disabled (ICCR0:EN=0):
) is received and IBCR10:GACKE = 1.
H
2
CHAPTER 22 I C
2
C bus control registers
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