Fujitsu F2MC-8FX Hardware Manual page 364

CHAPTER 20 UART/SIO
The TDRE flag is set at the point indicated in the following figure if the preceding piece of transmit data
does not exist in the transmission shift register.
Figure 20.7-7 Setting Timing 1 for Transmit Data Register Empty Flag (TDRE) (When TXE is "1")
"1"
TXE
Writing of
transmit data
UO
TDRE
Transmission
interrupt
Figure 20.7-8 Setting Timing 2 for Transmit Data Register Empty Flag (TDRE)
TXE
Writing of
transmit data
UO
TDRE
Transmission
interrupt
Concurrent transmission and reception
In asynchronous clock mode (UART), transmission and reception can be performed independently.
Therefore, transmission and reception can be performed at the same time or even with transmitting and
receiving frames overlapping each other in shifted phases.
350
D0 D1
Data transfer from UART/SIO serial output data register (TDR) to transmission
shift register is performed in one machine clock (MCLK) cycle.
(When TXE Is Switched from "0" to "1")
D0
D2 D3
D1 D2 D3