Fujitsu F2MC-8FX Hardware Manual page 509

Table 27.3-2 Functional Description of Bits of Real Time Clock Control Register Lower
Bit name
PAU:
Bit7
Pause bit
CL:
Bit6
Counter latch bit
PS:
Bit5 Power save mode
selection bit
Bit4 Not used
INTS:
Bit3 Interrupt selection
bit
S2, S1:
Bit2 TPCLK output
Bit1 frequency selection
bits
OE:
Bit0 TPCLK output
enable bit
• Write "1" : Pause the operation of prescaler.
• Write "0" : Release the pause and resume the counting of prescaler from 0000H.
• Setting this bit to "1" only during time/date setting.
• Before settig time/date information, set PAU to "1" so as to avert simultanous updating
of the new entries in the counters.
• After setting time/date information, set PAU to "0".
• Write "0" : Reading SECR/MINR/HOUR/DAYR/DOWR/MONR/YEAR provide the
current date and time.
• Write "1": Reading SECR/MINR/HOUR/DAYR/DOWR/MONR/YEAR provide the
latched data and time only. Although the counters are still counting and updating the date
and time, the latched date and time are preserved as long as this bit stands as "1".
• At the moment of changing this bit from "0" to "1", the current date and time are latched
into SECR/MINR/HOUR/DAYR/DOWR/MONR/YEAR.
• When "0" is written to the bit of value "1", the latched date and time are no longer
secured.
• Writing to /MINR/HOUR/DAYR/DOWR/MONR/YEAR/FFTR will clear this bit to "0".
• Write "1" : Select power save mode.
• Write "0" : Select non-power save mode.
• When this bit set to "1", the real time clock counters can still operate even the resource
clock has stopped.
• When this bit set to "1", all counters and registers (except for this PS control bit) cannot
be written or read.
• When this bit set to "0", all the real time clock counters become accessible (readable and
writable).
• Reading from this bit always return "0".
• Writing to this bit has not effect on operation.
• Write "0": The interrupt request signal is generated when any of the enabled
comparsion(s) matches.
• Write "1": The interrupt request signal is generated only when all of the enabled
comparison(s) matches.
• These bits select the TPCLK output frequency.
S2 S1
0 0
0 1
1 0
1 1
• Write "1" : the selected scaled-clock signal output to TPCLK.
• Write "0" : the selected scaled-clock signal does not output to TPCLK..
CHAPTER 27 REAL TIME CLOCK
Function
TPCLK output frequency slection bits
1Hz
0.1Hz
64Hz
1024Hz
495