Fujitsu F2MC-8FX Hardware Manual page 85

Table 6.8-1 State Transition Diagram (Transitions to and from Standby Modes)
State Transition
<1>
Normal operation from reset
state
<2>
(1)
Sleep mode
(2)
(3)
Stop mode
(4)
(5)
(6)
Timebase timer mode
(7)
(8)
Watch mode
(9)
After a reset, the device enters main clock mode.
If the reset is a power-on reset, the device always waits for the main clock oscillation stabilization
wait time to elapse.
When the clock mode before the reset is subclock mode, the device waits for the main clock
oscillation stabilization wait time to elapse. The device waits for it as well when the standby mode
is stop mode.
When the clock mode before the reset is main clock mode or main PLL clock mode and the
standby mode is other than stop mode, the device does not wait for the main clock oscillation
stabilization wait time to elapse even after entering a reset state in response to a watchdog reset,
software reset, or external reset.
The device enters sleep mode when "1" is written to the sleep bit in the standby control register
(STBC: SLP).
The device returns to the RUN state in response to an interrupt from a peripheral resource.
The device enters stop mode when "1" is written to the stop bit in the standby control register
(STBC: STP).
In response to an external interrupt, the device returns to the RUN state after waiting for the
oscillation stabilization wait time required for each clock mode.
When the device waits for a PLL oscillation stabilization wait time, it waits for the relevant
oscillation stabilization wait time or PLL oscillation stabilization wait time to elapse, whichever is
longer.
The device enters timebase timer mode when "1" is written to the watch bit in the standby control
register (STBC: TMD) in main clock mode or main PLL clock mode.
The device returns to the RUN state in response to a timebase timer interrupt, watch prescaler/
watch counter interrupt, or external interrupt.
When the clock mode is main PLL clock mode, the device waits for the main PLL clock oscillation
stabilization wait time to elapse. If the main PLL oscillation enable bit in the PLL control register
(PLLC: MPEN) contains "1", however, the device does not wait for that time to elapse even when
the clock mode is main PLL clock mode.
The device enters watch mode when "1" is written to the watch bit in the standby control register
(STBC: TMD) in subclock mode.
The device returns to the normal operating state in response to a watch prescaler/watch counter
interrupt or external interrupt..
CHAPTER 6 CLOCK CONTROLLER
Description
71