16-Bit Ppg Cycle Setting Buffer Registers (Pcsrh0, Pcsrl0) - Fujitsu F2MC-8FX Hardware Manual

17.5.2 16-bit PPG Cycle Setting Buffer Registers (PCSRH0,
PCSRL0)
The 16-bit PPG cycle setting buffer registers are used to set the cycle for the output
pulses generated by the PPG.

16-bit PPG Cycle Setting Buffer Registers (PCSRH0, PCSRL0)

Figure 17.5-3 16-bit PPG Cycle Setting Buffer Registers (PCSRH0, PCSRL0)
16-bit PPG cycle setting buffer register (upper) PCSRH0
Address
0FAC PCSRH0
H
16-bit PPG cycle setting buffer register (lower) PCSRL0
Address
0FAD PCSRL0
H
R/W: Readable/writable (Read value is the same as write value)
These registers form a 16-bit register which sets the period for the output pulses generated by the PPG. The
values set in these registers are loaded to the down-counter.
When writing to these registers, always use one of the following procedures.
• Use the "MOVW" instruction (use a 16-bit access instruction to write to the PCSRH0 register address).
• Use the "MOV" instruction and write to PCSRH0 first and PCSRL0 second.
If a down-counter load occurs after writing data to PCSRH0 (but before writing data to PCSRL0), the
previous valid PCSRH0/PCSRL0 value will be loaded to the down-counter. If the PCSRH0/PCSRL0
value is modified during counting, the modified value will become effective from the next load of the
down-counter.
• Do not set PCSRH0 and PCSRL0 to "00
Note:
If the down-counter load occurs after the "MOV" instruction is used to write data to PCSRL0 before
PCSRH0, the previous valid PCSRH0 value and newly written PCSRL0 value are loaded to the
down-counter. It should be noted that as a result, the correct period cannot be set.
bit15 bit14 bit13
CS15 CS14 CS13 CS12
R/W R/W R/W
bit7 bit6 bit5
CS07 CS06 CS05 CS04
R/W R/W R/W
bit12 bit11 bit10
CS11 CS10 CS09
R/W R/W R/W
bit4 bit3 bit2
CS03 CS02 CS01
R/W R/W R/W
", or PCSRH0 to "00
H
CHAPTER 17 16-BIT PPG TIMER
bit9 bit8 Initial value
CS08 11111111
R/W R/W
bit1 bit0 Initial value
CS00 11111111
R/W R/W
" and PCSRL0 to "01
H H
B
B
".
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