Fujitsu F2MC-8FX Hardware Manual page 281

Note also that an overflow toggles the timer output. The timer output initial value can be set by the timer
output initial value bit (T00CR1/T01CR1:SO).
When the timer stops operation, the timer output bit (TMCR0:TO1/TO0) holds the last value.
The value of the 8/16-bit composite timer 00/01 data register (T00DR/T01DR) must be nullified if an
interrupt occurs before the timer is activated (before "1" is written to the STA bit).
Figure 16.12-2 Operating Diagram of PWC Timer (Example of H-pulse Width Measurement)
Pulse input
(Input waveform to PWC pin)
Counter value
FFH
STA bit
IR bit
BF bit
Data transferred from
counter to T00/01DR
CHAPTER 16 8/16-BIT COMPOSITE TIMER
"H" width
Time
Cleared by program
Counter
operation
T00/01DR data register read
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