Block Diagram Of Mb95170J Series - Fujitsu F2MC-8FX Hardware Manual

1.4

Block Diagram of MB95170J Series

Figure 1.4-1 shows the block diagram of all MB95170J series.
Block Diagram of All MB95170J Series
RST
X0,X1
P95/X1A*
P94/X0A*
P00/AN00/INT00
to
P05/AN05/INT05
P06/AN06/INT06/SEG22
P07/AN07/INT07/SEG23
P10/UI0/EC0
P11/UO0/TO01
P12/UCK0/TO00
P13/PPG0/ADTG
P14/PPG1
P40/PPG2
P41/PPG3
P42/PPG4
P43/PPG5
*
* : It is general-purpose port in single clock product, and it is sub clock oscillation pin in dual clock product.
Figure 1.4-1 Block Diagram of All MB95170J Series
2
F MC-8FX CPU
Reset control
Hardware watchdog
RC oscillator
Clock control
Watch prescaler
Watch counter
External interrupt ch0 to ch7
10-bit A/D
converter
UART/SIO
8/16-bit compound
timer ch0
16-bit PPG 0
16-bit PPG 1
16-bit PPG 2
16-bit PPG 3
16-bit PPG 4
16-bit PPG 5
Port
Other pins
MOD, V , V C
CC SS,
DVcc, DVss x 2
ROM
RAM
Interrupt control
Wild register
2
I C C
8/16-bit compound
timer ch1
16-bit PPG 7
16-bit PPG 6
LCDC
External interrupt ch8 to ch11
RTC
Port
CHAPTER 1 DESCRIPTION
P50/SCL0
P51/SDA0
P60/SEG16 to P61/SEG17
P62/TO10/SEG18
P63/TO11/SEG19
P64/EC1/SEG20
P65/SEG21
P90/V3
P91/V2/PPG7
P92/V1/PPG6
PA0/COM0 to PA3/COM3
PB0/SEG00/TPCLK/CALPL
PB1/SEG01 to PB7/SEG07
PC0/TRG0/SEG08
to
PC7/TRG7/SEG15
PE4/INT10/SEG28
to
PE7/INT13/SEG31
9