CHAPTER 27 REAL TIME CLOCK
27.3.2
Real Time Clock Control Register Lower (RTCCRL)
The Real Time Control Register (Lower) is used to determine the frequency of TPCLK
and enable/disable TPCLK, latch counters' s values. and allow continuous counting
even the CPU proceeds to stand-by-mode.
Real Time Clock Control Register Lower (RTCCRL)
Figure 27.3-3 Real Time Clock Control Register Lower (RTCCRL)
Address
0FF1
H
R0/WX : Read 0 and write has no effect on operation
R/W : Readable and writable
-
: Unused
X
: Indeterminate
: Initial value
494
Bit 7
Bit 6
Bit 5
Bit 4
PAU
CL
PS
-
R/W
R/W
R/W
R0/WX
Bit 3
Bit 2
Bit 1
Bit 0
INTS
S2
S1
OE
R/W
R/W
R/W
R/W
OE
TPCLK output enable bit
0
Disable scaled clock signal to TPCLK
1
Enable scaled clock signal to TPCLK
S2
S1
TPCLK output frequency selection bits
0
0
0
1
1
0
1
1
INTS
Interrupt selection bit
Interrupt generated when any of the enabled
0
comparison(s) matches
Interrupt generated when all of the enabled
1
comparison(s) match
PS
Power save mode selection bit
0
Power save mode disabled
1
Power save mode enabled
CL
0
Counters are not being latched
1
Put counters' values into latch
PAU
0
Enable the counting of prescaler
1
Pause the counting of prescaler
Initial value
00X00000
B
1 Hz
0.1 Hz
64 Hz
1024 Hz
Count latch bit
PAUSE bit