Fujitsu F2MC-8FX Hardware Manual page 405

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Table 22.5-4 I C Clock Control Register (ICCR0)
Bit name
DMBP:
bit7
Divider-m bypass bit
bit6 Unused bit
EN:
2
bit5
I C operation enable
bit
CS4, CS3:
bit4
Clock-1 select bits
bit3
(Divider m)
bit2 CS2, CS1, CS0:
bit1 Clock-2 select bits
bit0 (Divider n)
Note: If the standby mode wakeup function is not used, disable I
watch mode.
This bit is used to bypass the divider m to generate the shift clock frequency.
Setting the bit to "1": Bypasses the divider m.
Setting the bit to "0": Sets the value set in CS3 and CS4 as the divider m value. (m = ICCR0:CS4, 3)
Note: Do not set this bit to "1" when divider n = 4 (ICCR0:CS2 to CS0 = 000
The value read is always "0".
An attempt to write to the bit is meaningless.
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• This bit enables I C interface operation.
Setting the bit to "1": Enables operation of the I
• This bit is set to "0" in the following cases:
- When "0" is written to this bit.
- When IBCR10:BER is "1".
Setting the bit to "0": Disables operation of the I
- AACKX, INTS, and WUE bits in the IBCR00 register
- All the bits in the IBCR10 register except the BER and BEIE bits
- All bits in the IBSR0 register
These bits set the shift clock frequency.
• Shift clock frequency (Fsck) is set as shown by the following equation:
Fsck =
(m x n + 2)
φ represents the machine clock frequency (MCLK).
Function
2
C interface.
2
C interface and clears the following bits to "0".
φ
2
C operation before switching the MCU to stop or
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CHAPTER 22 I C
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