Fujitsu F2MC-8FX Hardware Manual page 80

CHAPTER 6 CLOCK CONTROLLER
Table 6.7-1 Clock Mode State Transition Table
Current
State
<1>
Reset state Main clock
<2>
(1)
Subclock
(2)
Main clock
(3)
Main PLL clock
(4)
(5) Main clock
(6)
Main PLL
clock
Subclock
(7)
(8) Main clock
Subclock
(9) Main PLL clock
66
Next State
After a reset, the device waits for the main clock oscillation stabilization wait time to elapse
and enters main clock mode.
If the reset is a watchdog reset, software reset, or external reset caused in main clock mode
or main PLL clock mode, however, the device does not wait for the main clock oscillation
stabilization wait time to elapse.
The device enters subclock mode when the system clock selection bits in the system clock
control register (SYCC: SCS1, 0) are set to "00".
Note, however, that the device waits for the subclock oscillation stabilization wait time to
elapse before entering subclock mode either if the subclock has been stopped according to
the setting of the subclock oscillation stop bit in the system clock control register (SYCC:
SUBS) in main clock mode or if the subclock oscillation stabilization wait time has not
passed immediately after the power is turned on.
When the system clock selection bits in the system clock control register (SYCC: SCS1, 0)
are set to "11", the device enters main PLL clock mode after waiting for the main PLL clock
oscillation stabilization wait time.
Note, however, that the device does not wait for the main PLL clock oscillation stabilization
wait time to elapse if the main PLL clock has been oscillating according to the setting of the
main PLL clock oscillation enable bit in the PLL control register (PLLC: MPEN).
The device enters main clock mode when the system clock selection bits in the system clock
control register (SYCC: SCS1, 0) are set to "10".
The device enters subclock mode when the system clock selection bits in the system clock
control register (SYCC: SCS1, 0) are set to "00".
Note, however, that the device waits for the subclock oscillation stabilization wait time to
elapse before entering subclock mode either if the subclock has been stopped according to
the setting of the subclock oscillation stop bit in the system clock control register (SYCC:
SUBS) in main PLL clock mode or if the subclock oscillation stabilization wait time has not
passed immediately after the power is turned on.
When the system clock selection bits in the system clock control register (SYCC: SCS1, 0)
are set to "10", the device enters main clock mode after waiting for the main clock
oscillation stabilization wait time.
When the system clock selection bits in the system clock control register (SYCC: SCS1, 0)
are set to "11", the device enters main PLL clock mode after waiting for the main PLL clock
oscillation stabilization wait time or main clock oscillation stabilization wait time to elapse,
whichever is longer.
Description