Notes On Using Standby Mode - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 6 CLOCK CONTROLLER
6.8.1

Notes on Using Standby Mode

Even if the standby control register (STBC) sets standby mode, transition to the
standby mode does not take place when an interrupt request has been issued from a
peripheral resource. When the device returns from standby mode to the normal
operating state in response to an interrupt, the operation that follows varies depending
on whether the interrupt request is accepted or not.
Place at Least Three NOP Instructions Immediately Following a Standby Mode Setting
Instruction.
The device requires four machine clock cycles before entering standby mode after it is set in the standby
control register. During that period, the CPU executes the program. To avoid program execution during this
transition to standby mode, enter at least three NOP instructions.
The device operates normally if you place instructions other than NOP instructions. In that case, however,
note that the device may execute the instructions to be executed after being released from standby mode
before entering the standby mode and that the device may enter the standby mode during instruction
execution, which is resumed after the device is released from the standby mode (increasing the number of
instruction execution cycles).
Check That Clock-mode Transition has been Completed before Setting Standby Mode.
Before setting standby mode, make sure that clock-mode transition has been completed by comparing the
values of the clock mode monitor bit (SYCC: SCM1, 0) and clock mode setting bit (SYCC: SCS1, 0) in the
system clock control register.
An Interrupt Request may Suppress Transition to Standby Mode.
If an attempt is made to set a standby mode while an interrupt request with an interrupt level higher than
"11" has been issued, the device ignores the attempt to write to the standby control register and continues
instruction execution without entering the standby mode. The device does not enter the standby mode even
after having serviced the interrupt.
This behavior is the same as when interrupts are disabled by the interrupt enable flag (CCR:I) and interrupt
level bits in the condition code register (CCR:IL 1,0) of the CPU.
Standby Mode is Also Canceled when the CPU Rejects Interrupts.
When an interrupt request with an interrupt level higher than "11" is issued in standby mode, the device is
released from the standby mode regardless of the settings of the interrupt enable flag (CCR: I) and interrupt
level bits (CCR:IL1,0) of the condition code register of the CPU.
After being released from standby mode, the device services the interrupt when the CPU's condition code
register has been set to accept interrupts. If the register has been set to reject interrupts, the device resumes
processing from the instruction that follows the last instruction executed before entering the standby mode.
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