Reset Operation - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 7 RESET
7.1

Reset Operation

When a reset factor occurs, the CPU stops the current execution immediately and
enters the reset release wait state. When the device is released from the reset, the CPU
reads mode data and the reset vector from internal ROM (mode fetch). When the power
is turned on or when the device is released from a reset in subclock mode or stop
mode, the CPU performs mode fetch after the oscillation stabilization wait time has
passed.
Reset Factors
Resets are classified into five reset factors.
Table 7.1-1 Reset Factors
low-voltage detection reset
Clock supervisory reset
External reset
An external reset is generated upon "L" level input to the external reset pin (RST).
An externally input reset signal is accepted asynchronously via the internal noise filter and generates an
internal reset signal in synchronization with the machine clock to initialize the internal circuit.
Consequently, a clock is necessary for internal circuit initialization. Clock input is therefore necessary for
operation with an external clock.
Note, however, that external pins (including I/O ports and peripheral resources) are reset asynchronously.
Additionally, there are standard pulse-width values for external reset input. If the value is below the
standard, the reset may not be accepted. The standard value is listed on the data sheet. Please design your
external reset circuit so that this standard is met.
Software reset
Writing "1" to the software reset bit of the standby control register (STBC:SRST) generates a software
reset.
Watchdog reset
After the watchdog timer starts, a watchdog reset is generated if the watchdog timer is not cleared within a
preset amount of time.
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Reset Factor
External reset "L" level input to the external reset pin
"1" is written to the software reset bit (STBC: SRST) in the standby control
Software reset
register.
Watchdog reset The watchdog timer causes an overflow.
Power-on reset/
The power is turned on or the supply voltage falls below the detected voltage.
Oscillation stops abnormally, not caused by a predefined state transition.
Reset Condition