Condition Code Register (Ccr) - Fujitsu F2MC-8FX Hardware Manual

5.1.3

Condition Code Register (CCR)

The condition code register (CCR) in the lower eight bits of the program status (PS)
register consists of the bits (H, N, Z, V, and C) containing information about the
arithmetic result or transfer data and the bits (I, IL1, and IL0) used to control the
acceptance of interrupt requests.
Configuration of Condition Code Register (CCR)
RP
bit15 bit14 bit13 bit12 bit11 bit10 bit9
PS
R4 R3 R2
Half carry flag
Interrupt enable flag
Interrupt level bits
Negative flag
Zero flag
Overflow flag
Carry flag
The condition code register is a part of the program status (PS) register and therefore cannot be accessed
independently.
Bits Result Information Bits
Half carry flag (H)
This flag is set to "1" when a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 occurs as the result of
an operation. Otherwise, the flag is set to "0". Do not use this flag for any operation other than addition and
subtraction as the flag is intended for decimal-adjusted instructions.
Negative flag (N)
This flag is set to "1" when the value of the most significant bit is "1" as the result of an operation and set to
"0" if the value is "0".
Zero flag (Z)
This flag is set to "1" when the result of an operation is "0" and set to "0" otherwise.
Overflow flag (V)
This flag indicates whether an operation has resulted in an overflow, assuming the operand used for the
operation as an integer represented by a two's complement. The flag is set to "1" when an overflow occurs
and set to "0" otherwise.
Figure 5.1-5 Configuration of Condition Code Register
DP
bit8
DP2 DP1 DP0
R1 R0
CCR
bit7 bit6 bit5 bit4 bit3
H I IL1 IL0
CHAPTER 5 CPU
CCR Initial
bit2 bit1 bit0
00110000
N Z V C
value
B
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