Timebase Timer Control Register (Tbtc) - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 10 TIMEBASE TIMER
10.3.1

Timebase Timer Control Register (TBTC)

The timebase timer control register (TBTC) selects the interval time, clears the counter,
controls interrupts and checks the status.
Timebase Timer Control Register (TBTC)
Address
bit7
000A
TBIF
H
R(RM1),W R/W R0/WX R0/WX R0/WX
R(RM1),W : Readable/writable (Read value is different from write value, "1" is read by read-modfy-write instruction)
R/W : Readable/writable (Read value is the same as write value)
R0/WX : Undefined bit (Read value is "0", writting has no effect on operation)
R0,W : Write only (Writable, "0" is read)
- : Not used
: Initial value
162
Figure 10.3-2 Timebase Timer Control Register (TBTC)
bit6 bit5 bit4
TBIE
- -
TCLR
0
1
TBC1
0
0
1
1
TBIE
0
1
TBIE
0
1
bit3 bit2 bit1
- TBC1 TBC0 TCLR
R/W R/W R0,W
Timebase timer initialization bit
Read
"0" is always read
-
Interval time select bit
TBC0
(Main clock F
0 2
1 2
0
2
1
2
Timebase timer interrupt request enable bit
Disables output of interrupt request
Enables output of interrupt request
Timebase timer interrupt request flag bit
Read
Interval time has not
elapsed
Interval time has
elapsed
Initial value
bit0
00000000
B
Write
No change,
No effect on operation
Clears the counter of
timebase timer
= 4MHz)
CH
(512.0 μs)
10
x 2/F
CH
12
x 2/F (2.05 ms)
CH
14
x 2/F (8.19 ms)
CH
16
x 2/F (32.77 ms)
CH
Write
Clears bit
No change,
No effect on operation