Fujitsu F2MC-8FX Hardware Manual page 362

CHAPTER 20 UART/SIO
Start bit detection and confirmation of receive data during reception
The start bit is detected by a falling of the serial input followed by a succession of three "L" levels after the
serial data input is sampled according to the clock (BRCLK) signal provided by the dedicated baud rate
generator with the reception operation enable bit (RXE) set to "1". When the first "H, L, L, L" train is
detected in a BRCLK sample, therefore, the current bit is regarded as the start bit.
The frequency-quartered circuit is activated upon detection of the start bit and serial data is inputted to the
reception shift register at intervals of four periods of BRCLK.
When data is received, sampling is performed at three points of the baud rate clock (BRCLK) and data
sampling clock (DSCLK) and received data is confirmed on a majority basis when two bits out of three
match.
RXE
Serial data input
(UI0)
Baud rate clock
(BRCLK)
Start bit detection
Counter divided by 4
Data sampling clock
(DSCLK)
Reception shift register
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Figure 20.7-5 Start Bit Detection and Serial Data Input
Start bit
H L L L L
X
X
D0
0 1 2 3 0 1
Sampling at three points to determine "0" or "1" on a majority basis
when two bits out of three match
D0
D1
2 3
D1