Fujitsu F2MC-8FX Hardware Manual page 396

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CHAPTER 22 I C
2
I C Bus Control Register 1 (IBCR10)
bit7
Address
BER
0061 IBCR10
H
R(RM1),W
R/W : Readable/writable
(Read value is the same as write value)
R(RM1),W : Readable/writable (Read value is different from write
value, "1" is read by read-modfy-write instruction)
R0,W : Write only (Writable, "0" is read)
: Initial value
382
2
Figure 22.5-3 I C Bus Control Register 1 (IBCR10)
bit6 bit5 bit4 bit3
BEIE SCC MSS
DACKE GACKE
R/W R0,W R/W R/W
bit2 bit1 bit0
Initial value
INTE INT 00000000
R/W R/W R(RM1),W
Transfer completion interrupt request flag bit
INT
0 Data transfer not completed
1
1-byte data (including acknowledgment) transfer completed
INTE
Transfer completion interrupt enable bit
0
Disables data transfer completion interrupt requests.
1
Enables data transfer completion interrupt requests.
GACKE
General call address acknowledge enable bit
0
Disables general call address ACK.
1
Enables general call address ACK.
DACKE
Data acknowledge enable bit
0
1
MSS
0
1
Start condition generation bit
SCC
Read
0
Always "0"
1
Generates master-mode repeated start condition.
BEIE
Bus error interrupt request enable bit
0
Disables bus error interrupt requests.
1
Enables bus error interrupt requests.
Bus error interrupt request flag bit
BER
0
1
Invalid start/stop condition detected
B
Read
Disables data ACK.
Enables data ACK.
Master/slave select bit
Selects slave mode.
Selects master mode.
Write
Unchanged
Read
No bus error
Write
Clear
Unchanged
Write
Clear
Unchanged