Fujitsu F2MC-8FX Hardware Manual page 84

CHAPTER 6 CLOCK CONTROLLER
Figure 6.8-2 Standby Mode State Transition Diagram (Single System Clock Product)
Stop mode
Timebase timer
mode
70
(3)
(4)
Main clock/main
PLL clock oscillation
stabilization wait
time
(6)
Main PLL clock
(7)
oscillation stabiliza-
tion wait time
Power on
Reset state
<2>
<1>
Main clock oscillation
stabilization wait time
Normal (RUN) state
(1)
(5)
(2)
Reset occurs in each state.
Sleep mode