Fujitsu F2MC-8FX Hardware Manual page 387

Clock selector, clock divider, and shift clock generator
This circuit uses the machine clock to generate the shift clock for the I
Start/stop condition generation circuit
When a start condition is transmitted with the bus idle (SCL0 and SDA0 at the "H" level), a master starts
communications. When SCL0 = "H", a start condition is generated by changing the SDA0 line from "H" to
"L". The master can terminate its communication by generating a stop condition. When SCL0 = "H", a stop
condition is generated by changing the SDA0 line from "L" to "H".
Start/stop condition detection circuit
This circuit detects a start/stop condition for data transfer.
Arbitration lost detection circuit
This interface circuit supports multi-master systems. If two or more masters attempt to transmit at the same
time, the arbitration lost condition (if logic level "1" is sent when the SDA0 line goes to the "L" level)
occurs. When the arbitration lost is detected, IBCR00:ALF is set to "1" and the master changes to a slave
automatically.
Slave address comparison circuit
The slave address comparison circuit receives the slave address after the start condition to compare it with
its own slave address. The address is seven-bit data followed by a data direction (R/W) bit in the eighth bit
position. If the received address matches the own slave address, the comparison circuit transmits an
acknowledgment.
IBSR0 register
The IBSR0 register shows the status of the I
IBCR registers (IBCR00, IBCR10)
The IBCR registers are used to select the operating mode and to enable or disable interrupts,
acknowledgment, general call acknowledgment, and the function to wake up the MCU from standby mode.
ICCR0 register
The ICCR0 register is used to enable I
IAAR0 register
The IAAR0 register is used to set the slave address.
IDDR0 register
The IDDR0 register holds the transmit or receive shift data or address. When transmitted, the data or
address written to this register is transferred from the MSB to the bus.
Input Clock
2
I C uses the machine clock as the input clock (shift clock).
2
C interface.
2
C interface operations and select the shift clock frequency.
CHAPTER 22 I
2
C bus.
2
C
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