Fujitsu 8FX Hardware Manual page 495

MB95630H Series
When 5-bit to 8-bit serial data is received by the reception shift register, the received data is
transferred to the UART/SIO serial input data register ch. n (RDRn) and the next piece of serial
data can be received.
When the RDRn register stores data, the receive data register full flag bit (RDRF) is set to "1".
A receive interrupt occurs the moment the RDRF bit is set to "1" when the receive interrupt
enable bit (RIE) contains "1".
To read received data, read it from the RDRn register after checking the overrun error flag bit
(OVE) in the UART/SIO serial status and data register ch. n (SSRn).
When received data is read from the RDRn register, the RDRF bit is cleared to "0".
Figure 22.6-12 8-bit Reception of Synchronous Clock Mode
UCKn
UIn
Read to RDRn
RDRF
Operation when receive error occurs
When an overrun error (OVE = 1) occurs, received data is not transferred to the RDRn
register.
Overrun error (OVE = 1)
Upon completion of reception for serial data, the OVE bit is set to "1" if the RDRF bit has
been set to "1" by the reception for the preceding piece of data.
UCKn
D0 D1 ... D6 D7
UIn
Read to
RDRn
RDRF
OVE
MN702-00009-2v0-E
D0 D1 D2 D3 D4 D5 D6 D7
Figure 22.6-13 Overrun Error
...
D0 D1 ... D6 D7
FUJITSU SEMICONDUCTOR LIMITED
22.6 Operations and Setting Procedure Example
Interrupt to interrupt controller
...
D0 D1 ...
CHAPTER 22 UART/SIO
...
D6 D7
473