8/16-Bit Ppg Timer N1/N0 Duty Setup Buffer Register (Pdsn1/Pdsn0) - Fujitsu 8FX Hardware Manual

CHAPTER 18 8/16-BIT PPG
18.7 Registers
18.7.4 8/16-bit PPG timer n1/n0 Duty Setup Buffer
Register (PDSn1/PDSn0)
The 8/16-bit PPG timer n1/n0 duty setup buffer register (PDSn1/PDSn0) sets the
duty of the PPG output.
■ Register Configuration
PDSn1
bit 7
Field DH7
Attribute R/W
Initial value 1
PDSn0
bit 7
Field DL7
Attribute R/W
Initial value 1
■ Register Functions
The PDSn1 and PDSn0 registers set the duty of the PPG output ("H" pulse width when normal
polarity).
• In 16-bit PPG mode, PDSn1 serves as the upper 8 bits while PDSn0 serves as the lower 8
bits.
• In 16-bit PPG mode, write the upper bits before the lower bits. When only the upper bits are
written, the previously written value is reused in the next load. Writing data to PDSn0 also
updates PDSn1 at the same time.
• PDSn1 and PDSn0 are initialized upon reset.
• To set the duty to 0%, select "0x00".
• To set the duty to 100%, set it to the same value as the 8/16-bit PPG timer n1/n0 cycle setup
register (PPSn0, PPSn1).
• When the 8/16-bit PPG timer n0/n1 duty setup register (PDS) is set to a larger value than
the setting value of the 8/16-bit PPG cycle setup buffer register (PPS), the PPG output
becomes "L" output in the normal polarity (when the output level inversion bit of 8/16-bit
PPG output inversion register is "0").
• If the duty settings are modified during operation, the modified value will be effective from
the next PPG cycle.
326
6 5
DH6 DH5
R/W R/W
1 1
6 5
DL6 DL5
R/W R/W
1 1
FUJITSU SEMICONDUCTOR LIMITED
4 3
DH4 DH3
R/W R/W
1 1
4 3
DL4 DL3
R/W R/W
1 1
MB95630H Series
2 1
DH2 DH1
R/W R/W
1 1
2 1
DL2 DL1
R/W R/W
1 1
MN702-00009-2v0-E
0
DH0
R/W
1
0
DL0
R/W
1