Fujitsu 8FX Hardware Manual page 184

CHAPTER 11 8/16-BIT COMPOSITE TIMER
11.14 Registers
[bit3:0] F[3:0]: Timer operating mode select bits
These bits select the timer operating mode.
The PWM timer function (variable-cycle mode; F[3:0] = 0b0100) is set by either the Tn0CR0 (timer n0)
register or Tn1CR0 (timer n1) register. If one of the timers starts operating (Tn0CR1/Tn1CR1: STA= 1), the
F[3:0] bits of the other timer are automatically set to "0b0100".
With the 16-bit operation having been selected (TMCRn:MOD = 1), if the composite timer starts operating
using the PWM timer function (variable-cycle mode) (Tn0CR1/Tn1CR1:STA = 1), the MOD bit is set to "0"
automatically.
Write access to these bits is nullified in timer operation (Tn0CR1/Tn1CR1:STA = 1).
bit3:0
Writing "0000"
Writing "0001"
Writing "0010"
Writing "0011"
Writing "0100"
Writing "0101"
Writing "0110"
Writing "0111"
Writing "1000"
Writing "1001"
Writing "1010"
Writing "1011"
Writing "1100"
Writing "1101"
Writing "1110"
Writing "1111"
162
Interval timer (one-shot mode)
Interval timer (continuous mode)
Interval timer (free-run mode)
PWM timer (fixed-cycle mode)
PWM timer (variable-cycle mode)
PWC timer (H pulse = rising edge to falling edge)
PWC timer (L pulse = falling edge to rising edge)
PWC timer (cycle = rising edge to rising edge)
PWC timer (cycle = falling edge to falling edge)
PWC timer (H pulse = rising edge to falling edge; cycle = rising edge to rising edge)
Input capture (rising edge, free-run counter)
Input capture (falling edge, free-run counter)
Input capture (both edges, free-run counter)
Input capture (rising edge, counter clear)
Input capture (falling edge, counter clear)
Input capture (both edges, counter clear)
FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
Details
MN702-00009-2v0-E