16-Bit Mpg Output Control Register (Lower) (Opclr) - Fujitsu 8FX Hardware Manual

MB95630H Series
21.6.2 16-bit MPG Output Control Register (Lower)
(OPCLR)
The 16-bit MPG output control register (lower) (OPCLR) controls the output of
the OPT5 to OPT0 pins and the position detection interrupt.
■ Register Configuration
bit 7
Field PDIF
Attribute R/W
Initial value 0
■ Register Functions
[bit7] PDIF: Position detection interrupt request flag bit
This bit is the position detection interrupt request flag.
This bit is set to "1" when either one of the following conditions occurs:
• The CMPE bit in the IPCUR register is set to "1" and the SNI2 to SNI0 pins are compared with the RDA[2:0]
bits and they match.
• The CMPE bit is set to "0" and an effective edge is detected at SNI2 to SNI0 pins.
With the position detection interrupt already enabled (PDIE = 1), when the PDIF bit is set to "1", a position
detection interrupt is generated.
Writing "0" to this bit clears it. Writing "1" to this bit has no effect on operation.
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".
bit7
Reading "0"
Reading "1"
Writing "0"
Writing "1"
[bit6] PDIE: Position detection interrupt enable bit
This bit enables or disables the position detection interrupt.
When this bit is set to "1", and the position detection interrupt request flag bit (PDIF) is also set to "1", a
position detection interrupt is generated.
bit6
Writing "0"
Writing "1"
[bit5] OPE5: OPT5 output enable bit
This bit enables or disables OPT5 pin output.
bit5
Writing "0"
Writing "1"
MN702-00009-2v0-E
6 5
PDIE OPE5
R/W R/W
0 0
Indicates that no position detection interrupt request has been generated.
Indicates that a position detection interrupt request has been generated.
Clears this bit.
Has no effect on operation.
Disables the position detection interrupt.
Enables the position detection interrupt.
Disables OPT5 pin output.
Enables OPT5 pin output.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 21 MULTI-PULSE GENERATOR
4 3
OPE4 OPE3
R/W R/W
0 0
Details
Details
Details
21.6 Registers
2 1
OPE2 OPE1
R/W R/W
0 0
0
OPE0
R/W
0
429