MB95630H Series
4.2.1
Reset Source Register (RSRR)
The reset source register (RSRR) indicates the source of a reset generated.
■ Register Configuration
bit
7
Field
—
Attribute
—
Initial value
0
■ Register Functions
[bit7:5] Undefined bits
Their read values are always "0". Writing values to these bits has no effect on operation.
[bit4] EXTS: External reset flag bit
When this bit is set to "1", that indicates an external reset has occurred.
When any other reset occurs, this bit retains the value that has existed before such reset occurs.
A read access or a write access (writing "0" or "1") to this bit sets it to "0".
bit4
Read access
Being set to "1"
Write access
[bit3] WDTR: Watchdog reset flag bit
When this bit is set to "1", that indicates a watchdog reset has occurred.
When any other reset occurs, this bit retains the value that has existed before such reset occurs.
A read access or a write access (writing "0" or "1") to this bit sets it to "0".
bit3
Read access
Being set to "1"
Write access
[bit2] PONR: Power-on reset flag bit
When this bit is set to "1", that indicates a power-on reset or a low-voltage detection reset (optional) has
occurred.
When any other reset occurs, this bit retains the value that has existed before such reset occurs
The circuit is only available on certain products. Check the availability of the circuit in the device data sheet.
A read access or a write access (writing "0" or "1") to this bit sets it to "0".
bit2
Read access
Being set to "1"
Write access
MN702-00009-2v0-E
6
5
—
—
—
—
0
0
Sets this bit to "0".
Indicates that the an external reset has occurred.
Sets this bit to "0".
Sets this bit to "0".
Indicates that the a watchdog reset has occurred.
Sets this bit to "0".
Sets this bit to "0".
Indicates that the a power-on reset or a low-voltage detection reset (optional) has occurred.
Sets this bit to "0".
FUJITSU SEMICONDUCTOR LIMITED
4
3
EXTS
WDTR
R/W
R/W
X
X
Details
Details
Details
CHAPTER 4 RESET
4.2 Register
2
1
PONR
HWR
R/W
R/W
X
X
0
SWR
R/W
X
67