Fujitsu 8FX Hardware Manual page 487

MB95630H Series
● Reception in clock asynchronous mode (UART)
Use UART/SIO serial mode control register 1 ch. n (SMC1n) to select the serial data direction
(endian), parity/non-parity, parity polarity, stop bit length, character bit length, and clock.
Reception remains performed as long as the reception operation enable bit (SMC2n:RXE)
contains "1".
Upon detection of a start bit in receive data with the RXE bit set to "1", one frame of data is
received according to the data format set in UART/SIO serial control register 1 ch. n (SMC1n).
When the reception of one frame of data has been completed, the received data is transferred to
the UART/SIO serial input data register ch. n (RDRn) and the next frame of serial data can be
received.
When the RDRn register stores data, the receive data register full flag bit (SSRn:RDRF) is set
to "1".
A receive interrupt occurs the moment the RDRF bit is set to "1" when the receive interrupt
enable bit (SMC2n:RIE) contains "1".
Received data is read from the RDRn register after each error flag (PER, OVE, FER) in the
UART/SIO serial status and data register ch. n (SSRn) is checked.
When received data is read from the RDRn register, the RDRF bit is cleared to "0".
Note that modifying the SMC1n register during reception may result in unpredictable
operation. If the RXE bit is set to "0" during reception, the reception is immediately disabled
and initialization will be performed. The data received up to that point will not be transferred to
the serial input data register.
Figure 22.6-3 Receive Operation in Clock Asynchronous Mode (UART)
RXE
UIn
St
RDRn
read
RDRF
MN702-00009-2v0-E
D0 D1 D2 D3 D4 D5 D6
FUJITSU SEMICONDUCTOR LIMITED
22.6 Operations and Setting Procedure Example
D7 Sp Sp St
CHAPTER 22 UART/SIO
D0 D1 D2
465