Fujitsu 8FX Hardware Manual page 562

CHAPTER 26 DUAL OPERATION FLASH MEMORY
26.3 Invoking Flash Memory Automatic
Algorithm
Notes:
• Addresses in Table 26.3-1 are values on the CPU memory map. All addresses and
data are in hexadecimal notation. However, "X" is an arbitrary value.
• "U" in an address in Table 26.3-1 is not arbitrary, but represents the upper four bits (bit
15 to bit 12) of an address.
• The chip erase command is accepted only when programming data into all sectors has
been enabled. The chip erase command is ignored if the bit for any sector in the flash
memory sector write control register 0 (SWRE0) has been set to "0" (to disable
programming data to that sector).
■ Note on Issuing Commands
Enable programming data into a required sector before issuing the first command in the
command sequence table.
540 FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
MN702-00009-2v0-E