Fujitsu 8FX Hardware Manual page 519

MB95630H Series
● Clock selector, clock divider, and shift clock generator
This circuit uses the machine clock to generate the shift clock for the I
● Start/stop condition generation circuit
When a start condition is transmitted with the bus idle (SCLn and SDAn at the "H" level), a
master starts communications. When SCLn = "H", a start condition is generated by changing
the SDAn line from "H" to "L". The master can terminate its communication by generating a
stop condition. When SCLn = "H", a stop condition is generated by changing the SDAn line
from "L" to "H".
● Start/stop condition detection circuit
This circuit detects a start/stop condition for data transfer.
● Arbitration lost detection circuit
This interface circuit supports multi-master systems. If two or more masters attempt to transmit
at the same time, the arbitration lost condition (if logic level "1" is sent when the SDAn line
goes to the "L" level) occurs. When the arbitration lost is detected, IBCR0n:ALF is set to "1"
and the master changes to a slave automatically.
● Slave address comparison circuit
The slave address comparison circuit receives the slave address after the start condition to
compare it with its own slave address. The address is seven-bit data followed by a data
direction (R/W) bit in the eighth bit position. If the received address matches the own slave
address, the comparison circuit transmits an acknowledgment.
● IBSRn register
The IBSRn register shows the status of the I
● IBCR0n register and IBCR1n register
The IBCR0n register and the IBCR1n register are used to select the operating mode and to
enable or disable interrupts, acknowledgment, general call acknowledgment, and the function
to wake up the MCU from standby mode.
● ICCRn register
The ICCRn register is used to enable I
frequency.
● IAARn register
The IAARn register is used to set the slave address.
● IDDRn register
The IDDRn register holds the transmit or receive shift data or address. When transmitted, the
data or address written to this register is transferred from the MSB first to the bus.
■ Input Clock
2
The I C bus interface uses the machine clock as the input clock (shift clock).
MN702-00009-2v0-E
2
C bus interface operations and select the shift clock
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 24 I
2
C bus interface.
2
C BUS INTERFACE
24.2 Configuration
2
C bus.
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