Fujitsu 8FX Hardware Manual page 230

CHAPTER 14 LIN-UART
14.4 Interrupts
■ LIN Synch Field Edge Detection Interrupt (8/16-bit Composite Timer Interrupt)
Table 14.4-3 shows the control bits and interrupt sources of the LIN synch field edge detection
interrupt.
Table 14.4-3 Interrupt Control Bits and Interrupt Sources of LIN Synch Field Edge Detection
Interrupt
Interrupt Operating mode
Flag
request flag
register
bit
IR Tn0CR1
IR Tn0CR1
❍ : Bit to be used
× : Unused bit
● LIN synch field edge detection interrupt (8/16-bit composite timer interrupt)
In operating mode 3, the LIN synch field edge detection interrupt functions when the LIN-
UART performs LIN slave operation.
After a LIN synch break is detected, the internal signal (LSYN) is set to "1" at the first falling
edge of the LIN synch field, and set to "0" after the fifth falling edge. Between both falling
edges, a 8/16-bit composite timer interrupt is generated, provided that the 8/16-bit composite
timer has been configured to receive internal signals and detect rising edges and falling edges
and the 8/16-bit composite interrupt has been enabled.
The difference in the count values detected by the 8/16-bit composite timer (see Figure 14.4-1)
is equivalent to eight bits of the master serial clock. A new baud rate can be calculated from
this value. After set, a new baud rate becomes effective from the falling edge detected at the
next start bit set.
Figure 14.4-1 Baud Rate Calculation by 8/16-bit Composite Timer
Reception data
Internal signal
(LSYN)
8/16-bit
composite timer
Difference in count values = Capture value 2 - Capture Value 1
208
Interrupt source
0 1 2 3
First falling edge of the LIN
❍
× × ×
synch field
Fifth falling edge of the LIN
❍
× × ×
synch field
Start RDR RDR
bit bit0 bit1
FUJITSU SEMICONDUCTOR LIMITED
Interrupt source
enable bit
Tn0CR1:IE
LIN synch field
RDR RDR RDR RDR RDR
bit2 bit3 bit4 bit5 bit6
Data = 0x55
Capture value 1
MB95630H Series
Interrupt request flag
clear
Write "0" to Tn0CR1:IR
RDR Stop
bit7 bit
Capture value 2
MN702-00009-2v0-E